Parasitic gate capacitance of a field effect transistor (FET) reduces the performance of the transistor by reducing the switching speed. Specifically, the capacitive coupling of a gate electrode to adjacent circuit components limits the rate at which the voltage of the gate electrode may be changed. The delay in the changes in the gate voltage due to the capacitive coupling with adjacent circuit components is then reflected in an increase in a turn-on time and a turn-off time of the field effect transistor.
All transistors with a gate electrode, including junction field effect transistors (JFETs) and metal-oxide-semiconductor field effect transistors (MOSFETs), are prone to this type of parasitic capacitive coupling to adjacent circuit components by design. Particularly, high performance MOSFETs, in which contact vias to the source and drain regions are located close to the gate electrode to minimize the parasitic resistance of the source and drain region, suffer from high parasitic capacitance between the gate electrode and the contact vias due to their physical proximity.
Since both the gate electrode and the contact vias are physical structures, the parasitic capacitance may be reduced by scaling the dimensions of the gate electrode, the contact vias, or both. In one approach, the parasitic capacitance between the gate dielectric and a contact via may be reduced by reducing the height of the contact via. The reduction in the parasitic capacitance in this case is less than linear to the decrease in the height of the contact via since an M1 level (first level) metal wire moves close to the gate conductor correspondingly as the height of the contact via decreases, thereby increasing the parasitic capacitance between the gate conductor and the M1 line.
In another approach, the height of the gate conductor may be decreased to reduce the parasitic capacitance. In this case, the parasitic capacitance between the gate dielectric and the contact via is substantially linearly proportional to the height of the gate electrode. For example, the parasitic capacitance between a gate conductor line having a height of about 150 nm and a contact via located about 70 nm away from the gate conductor line, and having a silicon nitride gate spacer in between, is approximately 12 aF (1.2×10−17 F). By reducing the height of the gate conductor to 75 nm, the parasitic capacitance may be reduced to approximately 6 aF (6.0×10−18 F). Therefore, decreasing the height of the gate conductor is a more effective method of reducing the parasitic resistance than decreasing the height of contact vias.
In general, such reduction in the parasitic capacitance reduces the signal delay between two consecutive stages of a MOSFET circuit in which an output signal from a source or drain of the first stage MOSFET is fed into the gate electrodes of the second stage MOSFETs. While the degree of the reduction of the signal delay depends on the specifics of a circuit layout, it is estimated that the reduction of the parasitic capacitance from about 12 aF to 6 aF per pair of a gate electrode and a contact via, as described in the example above, leads to about a 3% reduction in the signal delay time for a two stage MOSFET circuit with a fanout of three, i.e., the first stage MOSFET drives three second stage MOSFETs, when the first MOSFET and each of the three second stage MOSFET are substantially of the same size.
Some structures for reducing the parasitic capacitance between the gate electrode and contact vias to achieve such improvements in circuit performance are known in the art. FIGS. 1-4 show an exemplary prior art structure intended to reduce parasitic capacitance between a gate electrode and contact vias at various stages of a manufacturing sequence.
Referring to FIG. 1, the exemplary prior art structure comprises a p-type MOSFET 99 and an n-type MOSFET 199, formed on a semiconductor substrate 10 and separated by shallow trench isolation 20. Each of the two MOSFETs (99, 199) at this stage comprises a gate dielectric 30 located directly on the semiconductor substrate 10, a silicon containing gate conductor 32, a disposable gate filler 34, and a gate spacer 40. The gate dielectric 30 may comprise silicon oxide, silicon oxynitride, high-K dielectric material, or a stack thereof. The silicon containing gate conductor 32 comprises polysilicon, or preferably, amorphous silicon and has a thickness of about 20 nm. The disposable gate filler 34 comprises silicon germanium alloy and has a thickness of about 80 nm. The gate spacer 40 typically comprises silicon nitride, which has a dielectric constant of about 7.5.
Referring to FIG. 2, source and drain regions 12 are formed by ion implantation into the semiconductor substrate 10. The disposable gate filler 34 is thereafter etched, preferably by a wet etch, to expose a top surface of the silicon containing gate conductor 32 and portions of inner sidewalls of the gate spacer 40.
Referring to FIG. 3, gate silicides 42 and source and drain silicides 44 are formed during a silicidation process. A first nitride liner 60 and a second nitride liner 61 are deposited on the source and drain silicides 44, inner sidewalls and outer sidewalls of the gate spacers 40, and on the gate silicides 42. The first and second nitride liners (60, 61) serve as mobile ion diffusion barriers, which block diffusion of mobile ions, such as Na+ and K+, from a middle-of-line (MOL) dielectric 70 or other back-end-of-line (BEOL) dielectric layers (not shown) into the semiconductor substrate 10. Furthermore, the first and second nitride liners (60, 61) may apply stress to underlying structures, and specifically, to the channels of the p-type MOSFET 99 and the n-type MOSFET 199. Highly preferably, the first nitride liner 60, which is located above the p-type MOSFET 99, applies a compressive uniaxial stress along the direction of the channel of the p-type MOSFET 99. Similarly, the second nitride liner 61, which is located above the n-type MOSFET 199, applies a tensile uniaxial stress along the direction of the channel of the n-type MOSFET 199.
The height of the gate electrode 48 of the prior art, which comprises the silicon containing gate conductor 32 and the gate silicide 42, has a height lower than the height of conventional gate electrode, which is substantially the same as the height of the gate spacers 40. According to the prior art, the parasitic capacitance between the gate electrode 48 and the contact vias 88 is thus reduced substantially in proportion to the height of the gate electrode 48.
The prior art described herein, however, has a disadvantage of reducing the stress applied by the first or second nitride liner (60 or 61) on the channel of the underlying MOSFET (99 or 199). Referring to FIG. 4, a magnified view of the p-type MOSFET 99 shows the structural components that determine the stress on the underlying channel 14. The arrows refer to the direction of the stress applied by the first nitride liner 60 to the underlying surfaces. Since the first nitride liner 60 contacts both the outer sidewalls and portions of the inner sidewalls of the gate spacer 40, a substantial fraction of the stress applied by the first nitride liner 60 to the outer sidewalls of the gate spacer 40 is cancelled by the stress applied by the same first nitride liner 60 to the portion of the inner sidewalls of the gate spacer 40. The net stress applied to the channel according the prior art is substantially proportional to the height of the gate electrode 48. The same effect occurs on the n-type MOSFET 199 with the difference being the direction of the applied stress.
While providing an advantageous effect of reduced parasitic capacitance between the gate electrode 48 and the contact vias 88, the prior art structure described above also produces a deleterious effect of reducing the stress applied to the channel of the MOSFET. The reduction in the stress, and the resulting reduction in the mobility of the minority carriers in the channel of the MOSFETs (99, 199) are detrimental to the performance of the prior art MOSFETs (99, 199).
Also, the dielectric constant of the nitride liners (60, 61) is about 7.5, which is a relatively high dielectric constant among semiconductor dielectric materials. The relatively high value of the dielectric constant of the nitride liners above the gate electrode 48 affects the parasitic capacitance adversely since the parasitic capacitance is also proportional to the dielectric constant of the material between the gate electrode 48 and the contact vias 88.
Therefore, there exists a need for a semiconductor structure in which the parasitic capacitance between a gate electrode and contact vias of a FET structure is reduced while providing substantially the same level of stress to the channel of the FET as conventional FETs and methods of manufacturing the same.
Further, there exists a need to reduce the dielectric constant of the material above the gate electrode while minimizing the size of the gate electrode and providing substantially the same level of stress to the channel of the FET as conventional FETs and methods of manufacturing the same.